EDN

Product Update: FPGA and PLD Design Tools

The ACTgen Macro Builder is a parameterized macro function generator that enables users to construct highly efficient counters, adders, and other structured blocks. Developed as a productivity and ...
EDN

Latest FPGA design tools from Lattice extend performance and productivity

The folks at Lattice Semiconductor have announced the immediate availability of their ispLEVER 7.1 FPGA design tool suite. This latest release delivers a number of new functional and ...
Linux Journal

Xilinx FPGA Design Tools for Linux

A field programmable gate array (FPGA) is a user-programmable piece of silicon constructed in very large-scale integration (VLSI) technology. The VLSI transistor-level detail is absolutely predefined ...
Yahoo

Blue Pearl Demos FPGA Design Tools for RTL Signoff, Improves QoR at ARM TechCon

The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs automate the ...
Design-Reuse

EDA tools and Design Methodology for multi-FPGA Designing/ Prototyping

As the cost of mask is increasing and the performance gap between FPGA and ASIC is reducing the FPGA is evolving a strong platform for not-only prototyping but also as a platform for real time design.
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Business Wire

Lattice Semiconductor and Synopsys Renew Partnership on FPGA Synthesis Tools

HILLSBORO, Ore.--(BUSINESS WIRE)--Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, and Synopsys, Inc. (NASDAQ: SNPS) today announced the extension of their ...
Design-Reuse

Design tools prepped for systems-on-programmable-chips

SAN MATEO, Calif. — As the major programmable-logic vendors introduce large, complex system-on-programmable-chip devices, some top-tier EDA vendors are scrambling to tailor their ASIC tool flows for ...
Electronic Design

Design Tool Streamlines SoC FPGA Application Creation

Xilinx’s SDSoC development environment turns code into FPGA logic. It targets Xilinx Zynq and Zynq MPSoC FPGA platforms. Xilinx’s SDSoC represents a major shift in support for SoC FPGAs. It opens FPGA ...
Semiconductor Engineering

Applying Machine Learning to EDA, FPGA Design Automation Tools

A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas Dallas. “With the recent advances in hardware ...
Electronic Design

FPGAs Ride Tools Into ASIC Territory

As their on-chip resources and gate count grow, more ASIC-like implementation flows push FPGAs into unlikely applications. When pondering your next-generation system design, you may ask yourself ...
Yahoo

REMINDER: Blue Pearl Demos FPGA Design Tools for RTL Signoff, Improves QoR at ARM TechCon

The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs automate the ...